As depicted in FIG. 1, when designing an LSI (Large Scale Integrated) circuit, first the layout of a macro itself as a functional block is designed in accordance with design rules (step 102). Next, the macro is placed on the LSI and inter-macro wiring is made (step 104). Finally, the entire LSI and the layout of the macro on the LSI are verified (step 106).
Since the layout within the macro is referred to when verifying the LSI layout, the amount of data to be handled increases, resulting in an increase in processing time. Further, macro terminals have to be connected on the LSI in order to place the macro on the LSI and make inter-macro wiring, but if there are not enough channels to connect the terminals, the macro cannot be placed and wired on the LSI.
Furthermore, even when the layout of the macro itself satisfies the design rules, there can occur cases where the relationship between the LSI wiring and the intra-macro wiring fails to satisfy the design rules when the macro is placed and wired on the LSI. For example, a rule violation associated with the parallel wiring of the LSI wiring and intra-macro wiring may be detected. In this way, problems that can occur due to interference between the layout within the macro and the LSI wiring when the macro is placed and wired on the LSI cannot be detected unless the macro is actually placed and wired on the LSI.
In designing the layout of the LSI, if an error occurs in the layout verification in relation to the intra-macro wiring, the intra-macro wiring cannot be modified without greatly affecting the design process. To address this, a method is employed that prohibits the use of wiring channels located adjacent to the intra-macro wiring during the LSI wiring so that the macro can be placed and wired on the LSI without having to be conscious of the layout within the macro. However, in designing the layout of the LSI, if the use of wiring channels located adjacent to the intra-macro wiring is prohibited, a problem occurs in that the number of channels available for use decreases, resulting in a degradation of wiring characteristics.
Patent document 1 cited below as a prior art document related to the present invention discloses an LSI design rule verification method wherein the verification of design rules is made by considering the hierarchy used in automatic layout. On the other hand, patent document 2 cited below discloses a functional macro design method that achieves connectivity having a high degree of wiring freedom without violating the design rules when connecting with other cells.    Patent document 1: Japanese Unexamined Patent Publication No. H05-102307    Patent document 2: Japanese Unexamined Patent Publication No. 2000-269341